WEBVTT 00:00:00.000 --> 00:00:05.360 Intel is, quite literally, about to flip the modern CPU upside down. 00:00:05.360 --> 00:00:09.000 Next year, they're going to be introducing a dramatic-sounding piece of technology 00:00:09.000 --> 00:00:12.200 called PowerVIA to their new processor lineups, 00:00:12.200 --> 00:00:16.080 and it looks like the wave of the future, not just for Intel CPUs, 00:00:16.080 --> 00:00:20.800 but products from other chip makers as well. Okay, Riley, you've got my attention. 00:00:20.800 --> 00:00:24.080 Tell me what's so great about it, is what you just said, probably. 00:00:24.080 --> 00:00:28.400 PowerVIA, or backside power delivery, to use a less Intel-specific term, 00:00:28.480 --> 00:00:32.560 is all about the tiny wires connected to your CPU's transistors, 00:00:32.560 --> 00:00:38.760 the parts that allow your CPU to think. Current CPUs have separate wires for power and data 00:00:38.760 --> 00:00:43.880 that both point downwards towards the socket. However, this method of CPU fabrication 00:00:43.880 --> 00:00:48.040 presents a few problems. One is that having power and signal wires 00:00:48.040 --> 00:00:53.120 so close to each other results in interference and, therefore, degraded performance. 00:00:53.120 --> 00:00:57.600 Another is that the wires used for power delivery have a natural resistance to them, 00:00:57.600 --> 00:01:03.160 and as we've put more and more transistors on our chips, we've had to make these wires smaller and smaller, 00:01:03.160 --> 00:01:08.320 which creates even more resistance, with the result being undesirable voltage drops 00:01:08.320 --> 00:01:12.560 that also limit performance. Trying to pack in so many small wires 00:01:12.560 --> 00:01:16.200 also increases cost and manufacturing complexity, 00:01:16.200 --> 00:01:19.520 as chip makers have to use very expensive lithography 00:01:19.520 --> 00:01:23.400 in order to meet their goals. So instead of just continuing to fight this problem 00:01:23.400 --> 00:01:26.560 more and more as transistors keep getting smaller, 00:01:26.600 --> 00:01:29.600 backside power delivery works smarter, not harder, 00:01:29.600 --> 00:01:32.680 and further separates power and signal wires. 00:01:32.680 --> 00:01:37.560 A chip built with backside power delivery has the signal wires coming out of the front side 00:01:37.560 --> 00:01:43.680 of the wafer the transistors sit on, with the power wires coming out of the bottom or backside. 00:01:43.680 --> 00:01:47.840 In the previous method we discussed, all wires come out of the front side, 00:01:47.840 --> 00:01:52.200 though, confusingly, usually the chip is flipped the other way, so the front side extends 00:01:52.200 --> 00:01:56.040 towards the CPU socket, with the transistors back near the heat spreader 00:01:56.040 --> 00:01:59.120 so they could be cooled down. It's all a little wacky. 00:02:00.080 --> 00:02:03.560 Chip engineers like to have fun, you know. With backside power delivery, 00:02:03.560 --> 00:02:07.640 although you do have a few signal wires still coming off the backside to allow the CPU 00:02:07.640 --> 00:02:11.400 to communicate with the rest of the system, the large majority of those signal wires 00:02:11.400 --> 00:02:15.080 are internal CPU transistor to transistor connections, 00:02:15.080 --> 00:02:19.720 which are placed on the front side. Intel has to polish the wafer down very thin 00:02:19.720 --> 00:02:23.560 in order to expose power connections to build out backside power delivery, 00:02:23.560 --> 00:02:27.760 meaning a dummy carrier wafer is bonded to the front side 00:02:27.760 --> 00:02:32.920 to give the whole stack structural support. It's like a really solid sandwich you should not eat. 00:02:32.920 --> 00:02:37.160 This mitigates the issues of interference and voltage drop we discussed earlier. 00:02:37.160 --> 00:02:42.800 Intel claims this results in a little over 5% higher core frequency on e-cores 00:02:42.800 --> 00:02:47.000 than would otherwise be possible, and gains on the higher performance P-cores 00:02:47.000 --> 00:02:50.120 should be similar. Another big advantage is because you're not trying to fit 00:02:50.120 --> 00:02:55.280 as many wires as you can into a certain space, manufacturing is cheaper and easier. 00:02:55.280 --> 00:02:58.840 Of course, since backside power delivery is a new fabrication method, 00:02:58.840 --> 00:03:03.800 there's an associated cost with rolling it out. But Intel says that the savings that come as a result 00:03:03.800 --> 00:03:07.600 of the overall easier manufacturing will more than offset this. 00:03:07.600 --> 00:03:12.720 Throw in the fact that Power Viya means you can fill more of the die with actual library cells, 00:03:12.720 --> 00:03:16.560 groups of transistors that process data, rather than blank space, 00:03:16.560 --> 00:03:21.080 and it isn't hard to see why Samsung and TSMC are also working to get their own chips 00:03:21.080 --> 00:03:25.320 featuring backside power delivery to market. I mean, this all sounds pretty great, 00:03:25.320 --> 00:03:29.800 but are there any downsides for the consumer? The one that has stuck out to some enthusiasts 00:03:29.800 --> 00:03:34.560 is that there are now quite a few layers of front side wiring separating the transistors 00:03:34.560 --> 00:03:39.360 from where a CPU cooler would sit. Intel claims that there's enough thermal conductivity 00:03:39.360 --> 00:03:42.360 through these layers to make cooling CPUs with Power Viya 00:03:42.360 --> 00:03:47.160 no more difficult than more traditional chips, but that remains to be seen. 00:03:47.160 --> 00:03:51.840 We should expect the first Intel chips with Power Viya to hit the market in mid-2024, 00:03:51.840 --> 00:03:55.920 with chips featuring backside power delivery from other manufacturers coming at least 00:03:55.920 --> 00:04:00.360 a couple years later. Comment down below if there are more topics in chip making you'd like us to tackle, 00:04:00.360 --> 00:04:05.480 but for now, all this talk about chips and wafers is really making me want some snacks. 00:04:05.480 --> 00:04:09.040 It's snack time for Riley. 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