Although transistors still keep on shrinking, it's getting more and more difficult to pack
as many of them on a chip as we'd like. Partial solutions to this, such as using chiplets
to reduce the rate of manufacturing defects and stacking transistors on top of each other
have been in vogue for a while now, but it might not be too surprising
that some manufacturers have decided to simply make the chip themselves bigger,
when in doubt, supersize. Now, I'm not saying that your next computer
might have a CPU that's so big it'll take up half the motherboard,
but when you get away from personal computers and start looking at chips
that we might see in data centers in the near future, you start seeing some pretty eye-watering stuff.
We're talking about designs like the Wafer Scale Engine 2 from Cerebrus,
currently the largest chip in the world. Built on a seven nanometer process,
it contains 850,000 cores
and is a whopping 21.5 centimeters or 8.5 inches long.
That's more total area than 25 Ryzen desktop CPUs.
Perhaps unsurprisingly, a chip this big and with this many transistors,
2.6 trillion, to be exact, requires a lot of power.
The Wafer Scale Engine 2 sucks down 15 kilowatts,
so if you were somehow able to drop this into your PC,
you'd need 15 1000 watt power supplies
just to keep it fit. And that's not even counting the rest of the system.
But despite this, the new design should actually result in power savings.
You see, data centers and supercomputers that do artificial intelligence processing
often have to use lots of separate chips, such as GPUs, spread across a large facility.
Having the same amount of computing power on just one physical chip is far more power efficient,
even if the power consumption rating of that chip is a lot higher than a typical GPU.
But there are other advantages to this approach, besides just saving energy.
You might be wondering why we aren't simply just sticking a bunch of chiplets onto one package instead
to make something like a really big version of an AMD Epic processor.
So as versatile as chiplets have been, they still suffer from having more latency
than one big monolithic processor. The little interconnects that move data
between chiplets as quick as they may be, and they are fast, are still slower
than if you physically put computing units directly adjacent to each other to form one big chip.
Ultimately, this means that huge monolithic chips can process more data than a system
with the same number of transistors spread out among multiple chips.
And when you consider just how much data has to be processed for AI applications
and scientific research, it makes a difference.
Wave for scale technology has already drawn interest from diverse industries,
including national intelligence and healthcare, but though it has some obvious advantages,
that doesn't necessarily mean that it's the silver bullet to large-scale compute challenges.
For instance, one big issue is the fact that these processors are designed to handle lots of data,
so they also need access to a lot of memory, and designs with chiplets and larger amounts of memory
built onto the same package may end up being more popular.
This is similar to what Tesla has done with their new D1 chip, which was developed in part
to help propel Tesla's self-driving AI technology.
The D1 chip itself is much smaller than the Wave for Scale engine,
but Tesla has included over 11 gigabytes of high-speed SRAM in an arrangement of 25 D1 chips
connected together to make a training tile that's bigger than your head.
And of course, making smaller chips reduces the amount of silicon you'll waste due to manufacturing errors,
as we mentioned earlier. But regardless of whether a particular company
is using Wave for Scale or an arrangement more like Tesla's,
putting a large amount of silicon on one plane may end up becoming an industry trend.
Because if America has taught us anything, it's that there's a deep human need to supersize.
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